PRY / Fibre sensing / FPGA and embedded software
OFDR/OVNA acquisition and embedded sequencing
A control, acquisition and demodulation chain for fibre measurement systems: from frequency sweeps to data used by supervision software, with FPGA implementations and MCU development.
/ context
The engineering problem
Coordinate synthesizers, analog-to-digital conversion and sample readout during a sweep while keeping timing and configuration consistent. The system must extract amplitude and phase, deliver results to supervision software and accommodate changes to its hardware and software architecture.
01
Coordinating the measurement chain
The work integrates the optical and RF front end with a digital carrier, embedded control and sequencing logic. In the Zynq-7000 generation, firmware configures the subsystems over SPI and a VHDL sequencer controls progression through the measurement points. Start, end-of-acquisition and memory-write signals coordinate the blocks. Separating configuration from automatic sequencing makes sweep parameters, delays and transition conditions explicit, providing a clearer connection between instrument behaviour and implementation. This structure also helps isolate the interfaces that must remain consistent when individual functions evolve.
02
Demodulation and supervision tools
Processing extracts amplitude and phase from the measurement and reference channels. The feasibility study for moving DSP from FPGA to software compares FFT and the Goertzel algorithm: Python supports numerical comparison on sample data, while the C implementation allows assessment of the processing load on the target processor. LabVIEW tools support acquisition, configuration and visualisation. Host command interfaces expose settings and status, connecting low-level functions with the laboratory workflow and providing the information needed to follow the acquisition and interpret its results.
03
MCU evolution and documentation
The subsequent STM32N657 implementation brings control, SPI/ADC acquisition and DSP modules onto an MCU running ThreadX and NetX. The work separates real-time functions from network commands and Linux host activities, keeping the responsibilities of each part clear. It includes application firmware, processing modules and tools for bench integration. Interface specifications, parameter maps and feasibility documentation accompany the sources. They record the design decisions, connect configuration to behaviour and provide a basis for later changes and verification across the different generations of the system.
Prototypes and development bench
/ output
What the work includes
- Digital carrier design and interface documentation
- FPGA sequencer logic and control firmware
- DSP modules and C/Python feasibility analysis
- MCU firmware and host command interfaces
- Acquisition and supervision tools
- Project documentation and bench-verification procedures
/ contact
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