VCU / Automotive / FPGA / acquisition and control
VCU FPGA — acquisition, DSP and host bridging
VHDL IP for sensor acquisition and conditioning in a vehicle control unit: ADC and FIR pipelines, knock and LVDT handling, phase alignment and connections to MCU/SoC hosts.
/ context
The engineering problem
Deliver different sensor signals to a control host with defined timing and consistent interfaces. The system needs acquisition, filtering and dedicated buffers, configurable coefficients and integration that allows host firmware to use the data and control the FPGA functions.
01
From sensors to the FPGA pipeline
The functions are developed in VHDL on Artix-7, organising ADC acquisition, FIR filtering and decimation into a hardware pipeline. The project includes paths for power-related signals, knock buffers and an LVDT chain. Each function makes its data format, acquisition rate and connection to downstream blocks explicit. This partitioning supports the integration of sources with different needs while keeping the elements that affect timing identifiable. Processing logic is therefore described together with the interfaces needed to access and use its results in the wider control system.
02
Data alignment and configuration
Synchronisation and phase alignment use the FPGA’s MMCM resources. Configurable parameters and registers connect pipeline behaviour to the settings required by the system. FIR coefficients can be reloaded through BlockRAM, while buffer maps and AXI interfaces define access to the information. The work includes descriptions of timing relationships, functional sections and project parameters. This allows the IP integrator to distinguish acquired data from configuration commands, understand the effect of settings and connect the hardware functions to the host firmware’s view of the system.
03
Host bridges and integration
An HSSL bridge connects the system to an AURIX host, while an SPI slave interface provides a further path to the SoC. The design considers RTL and host firmware together, defining registers, buffers and exchange methods. The Vivado flow includes IP integration, testbenches and timing analysis. Specifications and design notes accompany the code to guide integration into the VCU and verification of the individual functions. The result is a set of integrable blocks, with documentation of their interfaces and the conditions required for their use.
/ output
What the work includes
- VHDL IP and FPGA integration of VCU functions
- Acquisition and signal-conditioning pipeline
- Register and buffer maps for host firmware
- HSSL and SPI interfaces
- Project parameters and coefficient configuration
- Testbenches, specifications and timing-relationship notes
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