EXP-CSI / FPGA and interfaces
FPGA bridge for video streams
VHDL IP connecting an image sensor with LVDS output to a MIPI CSI-2 host processor, with data adaptation and clock-domain handling.
/ context
The engineering problem
An image sensor and the processor receiving its images can use different interfaces. The project needed an FPGA chain to convert the sensor’s LVDS stream into a MIPI CSI-2 output, organizing RAW10 data and addressing word alignment and transfers between clocks.
01
From the sensor to the host connection
We developed VHDL IP on Lattice CrossLinkPlus for a chain connecting the Onsemi PYTHON 1300 sensor to the Rockchip RK3576 SoC. The design includes the LVDS input, stream adaptation and MIPI CSI-2 transmitter. RAW10 defines how image data is handled along the path. The bridge makes the separation between the sensor interface, link processing and the output interface to the processor explicit.
02
Alignment and clock-domain crossing
The logic includes a 1:10 gearbox and word-alignment functions to reconstruct the correct organization of words in the received stream. FIFOs and clock-domain crossing blocks connect the sections of the chain operating with different timing references. These functions separate recovery of the data organization from transmission: they are the focus of integration between the sensor input, the internal bridge path and the MIPI CSI-2 output.
03
Integration and project tools
The work includes the IP core, technical documentation and the laboratory integration and test plan. Chain verification addresses the path from the LVDS sensor to the CSI-2 host, together with alignment functions and transfers between clock domains. The project tools are Clarity Designer, Diamond and Reveal. This case description focuses on the architecture and implemented blocks: stream sizing and integration remain tied to the combination of sensor, format and processor specified by the project.
/ output
What the work includes
- Bridge IP core
- Alignment and transfer logic
- Technical documentation
- Laboratory integration and test plan
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